This invention relates to clock multiplexers and more particularly to a clock multiplexer that may select between asynchronous clock signals without producing glitches in the selected clock signal output.
Depending upon design, a circuit may need to select its clock signal from a plurality of available clock signals that are asynchronous to one another. In such a situation, the transition from one clock signal to another may produce a clock signal having a xe2x80x9cglitchxe2x80x9d component. Such glitches include xe2x80x9cruntxe2x80x9d pulses, i.e., pulses whose high or low state has a duration shorter than the shortest corresponding pulse width of the available clock signals. Alternatively, a glitch may be just a spike or other transitory signal. Regardless of their form, glitches may wreak havoc because of the sensitivity of digital circuitry to clock specifications such as rising or falling clock edges.
To address the glitch problem, a number of clock selection circuits have been developed. Because of metastability problems, these circuits typically suffer from latency (multiple clock cycle delays to effect a clock switch). Also, these circuits typically demand a significant amount of die area. Accordingly, there is a need in the art for clock selection circuitry with improved delay and die area demands.
A clock multiplexer system selects between two clock input signals to produce a current output clock signal responsive to a selection signal. The input clock signal corresponding to the current output clock signal may be denoted as the current clock signal, and the remaining clock signal input may be denoted as the selected clock signal. Upon indication by the selection signal, the clock multiplexer system selects and passes the selected clock signal. This selection may occur in response to either a rising or falling edge in the clock input signals.
Should the selection be responsive to a falling edge in the clock input signals, the clock multiplexer system detects the first falling edge in the current clock signal subsequent to an indication in the selection signal. The clock output signal may then be held low while the clock multiplexer system waits for the first falling edge in the selected clock signal subsequent to the detection of the first falling edge in the current clock signal. When the clock multiplexer system detects this first falling edge in the selected clock signal, the clock multiplexer system unlatches the current output clock signal and passes the remaining clock signal.
Should the selection of the current clock signal output be responsive to a rising edge in the input clock signal, the clock multiplexer system detects the first rising edge in the current clock signal subsequent to a change in the selection signal. The clock output signal may then be latched high while the clock multiplexer system waits for the first rising edge in the selected clock signal subsequent to the detected rising edge in the current clock signal. When the rising edge in the selected clock signal is detected, the clock multiplexer system unlatches the clock signal output and passes the remaining clock signal.